1. Technical Field
This invention relates generally to methods, systems, machine readable media and apparatus for protecting intellectual property (“IP”). More specifically, this invention relates to techniques for limiting the use of IP in programmable logic devices and similar configurable devices.
2. Description of Related Art
Electronic design automation (“EDA”) is becoming increasingly complicated and time consuming, due in part to the increasing size and complexity of the devices designed by EDA tools. The design of even the simplest of these devices typically involves generation of a high level architecture and RTL design, logic simulation, logic synthesis, timing simulation, etc. Such devices include general purpose microprocessors and custom logic devices such as programmable logic devices, application specific integrated circuit (ASIC) emulators, application specific standard product (ASSP) emulators and/or ASSP devices that possess special or optional features that can be accessed by an authorized user.
A programmable logic device (“PLD”) is a programmable integrated circuit that allows the user of the circuit, using software control, to program the PLD to perform particular logic functions. A wide variety of these devices are manufactured by Altera Corporation of San Jose, Calif. When an integrated circuit manufacturer supplies a typical programmable logic device, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, can program the PLD to perform a particular function or functions required by the user's application. One or more of these programmed functions can be found in what is referred to commonly as a “core” within a PLD. These cores provide compartmentalized functional blocks that can be used within a programmed PLD or other logic device. Once a logic device such as a PLD is programmed with one or more of such cores, as well as any other logic as needed, the PLD can function in a larger system designed by the user just as though dedicated logic chips were employed.
One improvement in this field is the development of so-called “megafunctions” by companies such as Altera Corporation. Briefly, megafunctions are pre-designed, pre-tested, parameterized cores (or blocks of IP) which, when used, complement and augment existing design methodologies. When implementing complex system architectures, these megafunctions significantly enhance the design process. By using megafunctions, designers can focus more time and energy on improving and differentiating their system-level product, rather than re-designing frequently used functions.
As mentioned above, megafunctions are pre-designed, pre-verified parameterized implementations of system-level functions which reduce the customer's design task to creating the custom logic surrounding such commonly used system-level functions, dramatically shortening the design cycle by leveraging such existing intellectual property (“IP”), which can include proprietary apparatus, structures, techniques and methods applicable to the design field. Typically, an IP owner provides all of the files necessary to design with the megafunctions. Current practice allows designers to instantiate, compile and simulate a function to verify its operation, size and performance; however, programming files and other output files for implementing the design in hardware can be generated only with an authorization code provided when the megafunction is licensed.
A typical design cycle (using, for example, Altera's OpenCore technology) begins with a designer creating an initial block diagram and subsequently identifying any megafunctions available for use in the anticipated system. The designer then can identify and evaluate one or more specific megafunctions in terms of functionality and the range of parameterization available. After finding the appropriate megafunction(s), the designer installs the megafunction(s), completes the design and, using software, synthesizes and simulates the functionality and performance and estimates the hardware resources in the PLD required to implement the function within the anticipated circuitry and system.
However, software simulations of complex systems that incorporate IP frequently are limited in a number of respects. For example, due to the relatively slow speed of some software simulations, only a limited number of states might be testable by such software simulation. Because a hardware platform may run at much higher speeds than software simulations, a designer may need and/or want to test the design on a hardware platform as well.
In such applications, in order to fully validate and complete the system's design, the system frequently operates on a hardware prototype platform for a longer period of time than is practical for software simulation. After software simulation and synthesis, the IP owner authorizes the customer (via a license or other authorization logic) to generate programming data, such as a programming object file (a “POF” file) or an SRAM object file (a “SOF” file) of the design containing the IP, and to establish the hardware prototype. A hardware prototype platform is substantially identical to the production version of the hardware a designer intends to create. The hardware prototype can be a PLD or other device, or a system or subsystem of the total design to be created. As will be appreciated by those of ordinary skill in the art, the particulars of a hardware prototype are dependent upon the needs and circumstances of the project being undertaken by a designer and will vary widely. In the context of this disclosure, the term “hardware prototype” will mean any hardware platform suitable for evaluating and/or testing the hardware and available software for the system being designed. This hardware prototype also may be referred to herein as the “evaluation version” of a core, design or programmed device. The term “production hardware” means the desired final configuration of any hardware that the designer intends to achieve. Once this hardware prototype validation is completed, the customer can obtain from the IP owner production use authorization (such as a license), after which the IP used can be incorporated into specific devices and be put into production use.
Many IP owners have had to rely on legal contracts and/or other means to limit and control use of their IP on hardware platforms during prototype evaluation and during production use. Customers have been able to generate a file that could be used both for prototype evaluation as well as in production. Unauthorized use in production deprives the IP owner of compensation for use of its IP and inhibits the owner's control of its property. Attempts at technical measures to prevent unauthorized use of IP also have been only modestly effective.
One other solution to these problems is available using a technique that is the subject of U.S. patent application Ser. No. 09/823,700, entitled METHOD AND APPARATUS FOR PROVIDING A PROTECTED INTELLECTUAL PROPERTY HARDWARE, filed Mar. 30, 2001, assigned to Altera Corp., and is incorporated herein by reference in its entirety for all purposes. One or more aspects of the embodiments discussed in the above-cited application are incorporated in Altera's OpenCore Plus feature that is described in Altera Corporation's Application Note 176. Another solution to these problems is available using a technique that is the subject of U.S. patent application Ser. No. 10/339,170, entitled METHOD AND APPARATUS FOR CONTROLLING EVALUATION OF PROTECTED INTELLECTUAL PROPERTY IN HARDWARE, filed Jan. 7, 2003, assigned to Altera Corp., and is also incorporated herein by reference in its entirety for all purposes. In the systems discussed in the above-cited applications, various techniques enable potential users of PLDs to evaluate proprietary IP in hardware and thus permit improved development of digital systems and devices by designers while protecting the interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, that system provides to an end customer IP hardware which is suitable for prototype evaluation, but unusable for production purposes.
Techniques that permit full use of IP cores and the like while protecting the proprietary interests of the owners of the intellectual property incorporated in such designs, systems and devices would represent a significant advancement in the art. Moreover, techniques that allow the IP owner to limit the number of instances of a given IP core available to unlicensed users would represent a significant advancement in the art.